1. Technical Field
The present invention relates generally to the area of cache architectures for computer systems. Specifically, the present invention relates to a cache system that allows for the existence of cache lines for storing trace data and other empirical information, in which these particular cache lines are not written back to main memory.
2. Description of the Related Art
Current processors generate and collect a multitude of data intended to improve performance of a computer system. This includes performance monitoring data (e.g., profile data), branch prediction data, performance monitor data, pre-decoded instruction information, branch history information, branch prediction tables, and the like. Some of this data is stored in dedicated arrays or tables (e.g., profile data tables, branch history tables, or branch target address caches), while other data is stored in conjunction with instructions in the L1 (Level 1) instruction cache (such as pre-decode information, or in some instances, a secondary level of branch prediction information).
Additional data that can be collected and exploited continues to be discovered, so this trend of collecting and storing data for use in decision making is an increasing phenomenon. As the amount of data to be stored exceeds the size of the available dedicated arrays, these data are today usually discarded and later regenerated. In some cases, useful information may become lost, as branch prediction information must be reacquired in toto. In other instances, the data can be regenerated, but at the cost of spending additional time or power in recomputing the information. A cost/benefit tradeoff may result, as the value of the information collected is exceeded by the area cost or design/verification costs associated with enabling the information to be collected.
In some instances, a dedicated auxiliary storage hierarchy can be introduced to store this information, but at the cost of additional silicon area and design/test complexity. Some examples of existing technology using such a dedicated auxiliary storage hierarchy may be found in U.S. Pat. No. 4,679,141 (POMERENE et al.) 1987-07-07 and in processor cores developed by manufacturers Advanced Micro Devices, Inc. (the “Hammer” core) and Intel Corporation (Itanium 2).
One of the primary reasons why existing processor designs have utilized a dedicated auxiliary storage hierarchy is that it is generally advantageous to correlate processor metadata to the address of the data or instructions that relate to such metadata. For example, metadata relating to an instruction that causes a condition to occur in a processor should preferably be associated in some form with the address of the underlying instruction. The most straightforward way to do this is to give the metadata the same numerical address as that of the underlying instruction. The problem with this is, however, that it precludes storing the metadata and the underlying data or instruction in the same cache structure, since the two pieces of data would have conflicting storage addresses in the cache. Since the metadata is of minimal value without the underlying data or instructions it references, it becomes necessary, then, to either create a separate cache hierarchy to store the metadata or to use “hidden bits” or other forms of ancillary storage to store the metadata.
Therefore, what is needed is a means of providing better storage capabilities for data that is useful, but not necessarily critical, without adding significant system cost. A method of allowing data and processor metadata to coexist in a unified cache hierarchy without the use of such auxiliary data storage constructs as “hidden bits” is also needed. It would also be advantageous to be able to dynamically adapt such metadata storage to immediate performance and resource requirements during processor operation. The present invention provides a solution to these and other problems, and offers other advantages over previous solutions.